Power module with integrated surge voltage limiting element

ABSTRACT

One or more embodiments provide a power module that includes a high-side power transistor; a low-side power transistor coupled to the high-side power transistor, the low-side power transistor including a first load path terminal through which a load current enters the low-side power transistor and a second load path terminal through which the load current exits the low-side power transistor; a gate driver integrated circuit (IC) configured to drive the high-side power transistor and/or the low-side power transistor; a leadframe having a low-side voltage pin configured to be coupled to a low-side voltage source; a surge voltage limiting element coupled between the second load path terminal of the low-side power transistor and the low-side voltage pin; and a module package, where the high-side power transistor, the low-side power transistor, the gate driver IC, the leadframe, and the surge voltage limiting element are encapsulated in the module package.

FIELD

The present disclosure relates generally to power modules, and, inparticular, to power modules with an integrated surge voltage limitingelement.

BACKGROUND

A high voltage (HV) gate driver circuit may include a low voltage (LV)gate driver used to drive a low-side transistor switch and an HV gatedriver used to drive a high-side transistor switch. Such gate drivercircuits may be susceptible to electrical overstress failures at thelow-side gate driver and low-side transistor switch due to a surgevoltage. For example, when a low-side transistor switch is turned on,current may flow through the low-side transistor switch and a shuntresistor coupled thereto. At this time, a surge voltage may be induceddue to stray inductance of a printed circuit board (PCB) pattern and theshunt resistor.

Therefore, an improved device capable of limiting the surge voltage andpreventing electrical overstress failures may be desirable.

SUMMARY

One or more embodiments provide a power module that includes a high-sidepower transistor; a low-side power transistor coupled to the high-sidepower transistor, the low-side power transistor including a first loadpath terminal through which a load current enters the low-side powertransistor and a second load path terminal through which the loadcurrent exits the low-side power transistor; a gate driver integratedcircuit (IC) configured to drive the high-side power transistor and/orthe low-side power transistor; a leadframe having a low-side voltage pinconfigured to be coupled to a low-side voltage source; a surge voltagelimiting element coupled between the second load path terminal of thelow-side power transistor and the low-side voltage pin; and a modulepackage, wherein the high-side power transistor, the low-side powertransistor, the gate driver IC, the leadframe, and the surge voltagelimiting element are encapsulated in the module package.

One or more embodiments provide a power circuit that includes a powermodule and a circuit external to the power module. The power moduleincludes a high-side power transistor; a low-side power transistorcoupled to the high-side power transistor, the low-side power transistorincluding a first load path terminal through which a current enters thelow-side power transistor and a second load path terminal through whichthe current exits the low-side power transistor; a gate driverintegrated circuit (IC) configured to drive the high-side powertransistor and/or the low-side power transistor; a leadframe having alow-side voltage pin coupled to a low-side voltage source, and a furtherpin coupled to the second load path terminal of the low-side powertransistor and to a negative power supply rail; a surge voltage limitingelement coupled between the low-side voltage pin and the further pin,wherein the surge voltage limiting element provides a first current pathfor a first portion of the current that flows through the low-side powertransistor; and a module package, wherein the high-side powertransistor, the low-side power transistor, the gate driver IC, theleadframe, and the surge voltage limiting element are encapsulated inthe module package; and a circuit external to the power module andcoupled to the further pin, wherein the circuit provides a secondcurrent path for a second portion of the current that flows through thelow-side power transistor.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments are described herein making reference to the appendeddrawings.

FIG. 1 is a schematic block diagram illustrating a motor controlactuator of a power semiconductor device according to one or moreembodiments;

FIG. 2 is a schematic block diagram of a power module according to oneor more embodiments;

FIGS. 3A and 3B are schematic block diagrams of a power module accordingto one or more embodiments;

FIG. 3C is a schematic block diagram of the power module shown in FIG.3A with additional external circuitry according to one or moreembodiments; and

FIGS. 4A-4C are top-views of schematic block diagrams of power modulesaccording to one or more embodiments.

DETAILED DESCRIPTION

In the following, details are set forth to provide a more thoroughexplanation of the exemplary embodiments. However, it will be apparentto those skilled in the art that embodiments may be practiced withoutthese specific details. In other instances, well-known structures anddevices are shown in block diagram form or in a schematic view ratherthan in detail in order to avoid obscuring the embodiments. In addition,features of the different embodiments described hereinafter may becombined with each other, unless specifically noted otherwise.

Further, equivalent or like elements or elements with equivalent or likefunctionality are denoted in the following description with equivalentor like reference numerals. As the same or functionally equivalentelements are given the same reference numbers in the figures, a repeateddescription for elements provided with the same reference numbers may beomitted. Hence, descriptions provided for elements having the same orlike reference numbers are mutually exchangeable.

In this regard, directional terminology, such as “top”, “bottom”,“below”, “front”, “behind”, “back”, “leading”, “trailing”, “above” etc.,may be used with reference to the orientation of the figures beingdescribed. Because parts of embodiments can be positioned in a number ofdifferent orientations, the directional terminology is used for purposesof illustration and is in no way limiting. It is to be understood thatother embodiments may be utilized and structural or logical changes maybe made without departing from the scope defined by the claims. Thefollowing detailed description, therefore, is not to be taken in alimiting sense.

It will be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present. Other words used to describe therelationship between elements should be interpreted in a like fashion(e.g., “between” versus “directly between,” “adjacent” versus “directlyadjacent,” etc.).

In embodiments described herein or shown in the drawings, any directelectrical connection or coupling, i.e., any connection or couplingwithout additional intervening elements, may also be implemented by anindirect connection or coupling, i.e., a connection or coupling with oneor more additional intervening elements, or vice versa, as long as thegeneral purpose of the connection or coupling, for example, to transmita certain kind of signal or to transmit a certain kind of information,is essentially maintained. Features from different embodiments may becombined to form further embodiments. For example, variations ormodifications described with respect to one of the embodiments may alsobe applicable to other embodiments unless noted to the contrary.

The term “substantially” may be used herein to account for smallmanufacturing tolerances (e.g., within 5%) that are deemed acceptable inthe industry without departing from the aspects of the embodimentsdescribed herein.

A sensor may refer to a component which converts a physical quantity tobe measured to an electric signal, for example, a current signal or avoltage signal. The physical quantity may, for example, be a current ora voltage at a shunt resistor in a single-shunt resistor system.

A signal processing circuit and/or a signal conditioning circuit mayreceive one or more signals from one or more components and performsignal conditioning or processing thereon. Signal conditioning, as usedherein, refers to manipulating a signal in such a way that the signalmeets the requirements of a next stage for further processing. Signalconditioning may include converting from analog to digital (e.g., via ananalog-to-digital converter), amplification, filtering, converting,biasing, range matching, isolation and any other processes required tomake a signal suitable for processing after conditioning.

Thus, a signal processing circuit may include an analog-to-digitalconverter (ADC) that converts the analog signal from the one or moresensor elements to a digital signal. The signal processing circuit mayalso include a digital signal processor (DSP) that performs someprocessing on the digital signal.

Many functions of modern devices in automotive, consumer and industrialapplications, such as converting electrical energy and driving anelectric motor or an electric machine, rely on power semiconductordevices. For example, Insulated Gate Bipolar Transistors (IGBTs), MetalOxide Semiconductor Field Effect Transistors (MOSFETs) and diodes, toname a few, have been used for various applications including, but notlimited to switches in power supplies and power converters.

A power semiconductor device usually comprises a semiconductor structureconfigured to conduct a load current along a load current path betweentwo load terminal structures or load electrodes (e.g., thesource/emitter and the drain/collector) of the device. Further, the loadcurrent path may be controlled by means of a control electrode,sometimes referred to as gate electrode. For example, upon receiving acorresponding control signal from, e.g., a driver unit, the controlelectrode may set the power semiconductor device in one of a conductingstate or a blocking state. A control signal may by a voltage signal or acurrent signal having a controlled value.

A power transistor, also referred to as a power switch or a transistorswitch, is a power semiconductor device that may be used to drive a loadcurrent. For example, an IGBT is turned “ON” or “OFF” by activating anddeactivating its gate terminal. Applying a positive input voltage signalacross the gate and the emitter will keep the device in its “ON” state,while making the input gate signal zero or slightly negative will causeit to turn “OFF”. There is a turn-on process and a turn-off process forswitching the power transistor on and off.

During the turn-on process, a gate driver integrated circuit (IC) may beused to provide (source) a gate current (i.e., an ON current) to thegate of the power transistor in order to charge the gate to a sufficientvoltage to turn on the device. In particular, current Io+ is a gatedriver output current used to rise (i.e., charge) the gate of the powertransistor during a turn on transient. Thus, it is used to turn on thepower transistor.

In contrast, during the turn-off process, the gate driver IC is used todraw (sink) a gate current (i.e., an off current) from the gate of thepower transistor in order to discharge the gate sufficiently to turn offthe device. Current Io− is a gate driver output current used todischarge the gate of the power transistor during a turn off transient.Thus, it is used to turn off the power transistor.

A voltage pulse may be output from the gate driver IC as the controlsignal according to a pulse width modulation (PWM) scheme. Thus, thecontrol signal may be switched between an ON voltage level and an OFFvoltage level during a PWM cycle for controlling a power transistor.This in turn charges and discharges the gate voltage to turn on and offthe power transistor, respectively.

In particular, the gate of a power transistor is a capacitive load, andthe turn ON current (i.e., gate source current) and the turn OFF current(i.e., gate sink current) are specified as the initial current when aswitching event is initiated. During a turn OFF event, after some smallamount of time (small compared to the PWM period), the gate currentdecreases and reaches a zero value when the gate reaches 0V. During aturn ON event, after some small amount of time (small compared to thePWM period), the gate current decreases and reaches a zero value whenthe gate reaches 15V.

Transistors may include Insulated Gate Bipolar Transistors (IGBTs) andMetal Oxide Semiconductor Field Effect Transistors (MOSFETs) (e.g., SiMOSFETs or SiC MOSFETs). While IGBTs may be used as an example in theembodiments below, it will be appreciated that MOSFETs may besubstituted for the IGBTs and vice versa. In this context, whensubstituting a MOSFET for an IGBT, a MOSFET's drain may be substitutedfor an IGBT's collector, the MOSFET's source may be substituted for theIGBT's emitter, and the MOSFETs drain-source voltage V_(DS) may besubstituted for the IGBT's collector-emitter voltage V_(CE) in any oneof the examples described herein. Thus, any IGBT module may besubstituted by a MOSFET module and vice versa.

Specific embodiments described in this specification pertain to, withoutbeing limited thereto, a power semiconductor device that may be usedwithin a power converter or a power supply. Thus, in an embodiment, thepower semiconductor device may be configured to carry a load currentthat is to be supplied to a load and/or, respectively, that is providedby a power source. For example, the semiconductor device may compriseone or more power semiconductor cells, such as a monolithicallyintegrated diode cell, and/or a monolithically integrated transistorcell. Such diode cell and/or such transistor cells may be integrated ina power semiconductor module.

Power semiconductor devices that include transistors which are suitablyconnected to form half-bridges are commonly used in the field of powerelectronics. For example, half-bridges may be used for driving electricmotors or switched mode power supplies.

For example, a multi-phase inverter is configured to provide multi-phasepower by supplying multiple phase loads (e.g., a three-phase motor). Forinstance, three-phase power involves three symmetrical sine waves thatare 120 electrical degrees out of phase with one another. In a symmetricthree-phase power supply system, three conductors each carry analternating current (AC) of the same frequency and voltage amplituderelative to a common reference but with a phase difference of one thirdthe period. Due to the phase difference, the voltage on any conductorreaches its peak at one third of a cycle after one of the otherconductors and one third of a cycle before the remaining conductor. Thisphase delay gives constant power transfer to a balanced linear load. Italso makes it possible to produce a rotating magnetic field in anelectric motor.

In a three-phase system feeding a balanced and linear load, the sum ofthe instantaneous currents of the three conductors is zero. In otherwords, the current in each conductor is equal in magnitude to the sum ofthe currents in the other two, but with the opposite sign. The returnpath for the current in any phase conductor is the other two phaseconductors. The instantaneous currents result in a current space vector.

A three-phase inverter includes three inverter legs, one for each of thethree phases, and each inverter leg is connected to a direct current(DC) voltage source in parallel to each other. Each inverter legincludes a pair of power transistors, for example, arranged in ahalf-bridge configuration for converting DC to AC. In other words, eachinverter leg includes two complementary transistors (i.e., a high-sidetransistor and a low-side transistor) connected in series and whichswitch on and off complementary to the each other for driving a phaseload. However, multi-phase inverters are not limited to three phases,and may include two phases or more than three phases, with an inverterleg for each phase.

FIG. 1 is a schematic block diagram illustrating a motor controlactuator 100 of a power semiconductor device according to one or moreembodiments. In particular, the motor control actuator 100 includes apower inverter 1 and an inverter control unit 2. The inverter controlunit 2 behaves as a motor control unit and thus may also be referred toas a motor controller or a motor control IC. The motor control unit maybe a monolithic IC or may be split into a microcontroller and a gatedriver on two or more ICs.

The motor control actuator 100 is further coupled to a three-phase motorM, that includes three phases U, V, and W. The power inverter 1 is athree-phase current generator configured to provide three-phase power bysupplying three phase currents to drive the motor M. It will be furtherappreciated that the power inverter 1 and the inverter control unit 2may be placed on a same circuit board, or on separate circuit boards.

Deviations in both magnitude and phase may case a loss in power andtorque in the motor M. Therefore, the motor control actuator 100 may beconfigured to monitor and control the magnitude and phase of thecurrents supplied to the motor M in real-time to ensure the propercurrent balance is maintained based on a feedback control loop. Openloop motor control units also exist and may be implemented.

The power inverter 1 includes a switching array of six transistormodules 3 u+, 3 u−, 3 v+, 3 v−, 3 w+, and 3 w− (collectively referred toas transistor modules 3) arranged in complementary pairs. Eachcomplementary pair constitutes one inverter leg that supplies a phasecurrent to the three-phase motor M. Thus, each inverter leg includes anupper (high-side) transistor module 3 and a lower (low-side) transistormodule 3. Each transistor module may include one transistor, and mayalso include a diode (not shown). Thus, each inverter leg includes anupper transistor (i.e., a high-side switch) and a lower transistor(i.e., a low-side switch). Load current paths U, V, and W extend from anoutput of each inverter leg (i.e., the output of each half-bridge)located between complementary transistors and are configured to becoupled to a load, such as motor M. The power inverter 1 is coupled to aDC power supply 4 (e.g., a battery or a diode bridge rectifier) and tothe inverter control unit 2.

In this example, the inverter control unit 2 includes a motor controlcircuit and a gate driver circuit for controlling the switching array.In some examples, the inverter control unit 2 may be monolithic in whichthe motor control circuit and gate driver circuit are integrated onto asingle die. In other examples, the motor control circuit and gate drivercircuit may be partitioned as separate ICs. A “monolithic” gate driveris a gate driver on a single silicon chip and may be further made withspecific high voltage (HV) technology. Furthermore, the gate driver ICmay be integrated on the power inverter 1 to form a power module.

The motor controller IC performs the motor control function of the motorcontrol actuator 100 in real-time. Motor control function can includeeither controlling a permanent magnet motor or an induction motor andcan be configured as a sensorless control not requiring the rotorposition sensing, as a sensor based control with Hall sensors and/or anencoder device, or as a combination of both sensor based control (e.g.,used at lower rotor speeds) and sensorless control (e.g., used at higherrotor speeds).

For example, the inverter control unit 2 includes a controller anddriver unit 5 that includes a microcontroller unit (MCU) as the motorcontroller IC and a gate driver IC for generating driver signals forcontrolling the transistors of each transistor module 3. Thus, loadcurrent paths U, V, and W may be controlled by the controller and driverunit 5 by means of controlling the control electrodes (i.e., gateelectrodes) of the transistors 3. For example, upon receiving a controlsignal from the microcontroller, the gate driver IC may set acorresponding transistor in one of a conducting state (i.e., on-state)or a blocking state (i.e., off-state).

The gate driver IC may be configured to receive instructions, includingthe power transistor control signals, from the MCU, and turn on or turnoff respective transistors 3 in accordance with the receivedinstructions and control signals. For example, during the turn-onprocess of a respective transistor 3, the gate driver IC may be used toprovide (source) a gate current to the gate of the respective transistor3 in order to charge the gate. In contrast, during the turn-off process,the gate driver IC may be used to draw (sink) a gate current from thegate of the transistor 3 in order to discharge the gate.

The inverter control unit 2 or the controller and driver unit 5 itselfmay include a PWM controller, an ADC, a DSP, and/or a clock source(i.e., a timer or counter) used in implementing a PWM scheme forcontrolling the states of each transistor, and, ultimately, each phasecurrent provided on the respective load current paths U, V, and W.

In particular, the microcontroller of the controller and driver unit 5may use a motor control algorithm, such as a field-oriented control(FOC) algorithm, for providing current control in real-time for eachphase current output to a multi-phase load, such a multi-phase motor.Motor speed may further be controlled by adding a speed control loop ontop of FOC control. Thus, FOC may be considered as an inner control loopand a speed control loop may be considered as an outer control loop. Insome cases, motor position may be controlled using a third control loop(e.g., a position control loop) outside of the speed control loop.

For example, during FOC, a motor phase current should be measured suchthat an exact rotor position can be determined in real-time. Toimplement the determination of the motor phase current, the MCU 5 mayemploy an algorithm (e.g., space vector modulation (SVM), also referredas space vector pulse width modulation (SVPWM)) that uses single-shuntcurrent sensing.

Furthermore, the switches 3 (i.e., transistors) of the power inverter 1are controlled so that at no time are both switches in the same inverterleg turned on or else the DC supply would be shorted. This requirementmay be met by the complementary operation of the switches 3 within aninverter leg according to the motor control algorithm.

FIG. 2 is a schematic block diagram of a power module 200 according toone or more embodiments. The power module 200 includes a single-phasemotor drive stage 10 (i.e., an inverter leg) and a gate driver IC 20electrically coupled to the single-phase motor drive stage 10. However,the single-phase motor drive stage may be expanded to a multiple-phasemotor drive state by adding additional inverter legs. Both thesingle-phase motor drive stage 10 and the gate driver IC 20 areintegrated into a single package (not illustrated). Thus, the powermodule 200 is packaged as a single device.

The single-phase motor drive stage 10 includes a low-side transistor 11and a high-side transistor 12 that are controlled for supplying a loadcurrent I_(LOAD) to a one phase of a motor (not illustrated).Freewheeling diodes D1 and D2 coupled to their respective powertransistors 11 and 12 are also shown.

The gate driver 20 is a monolithic high voltage (HV) gate driver, thatincludes a low voltage (LV) gate driver 21 used to drive the low-sidetransistor switch 11 and an HV gate driver 22 used to drive thehigh-side transistor switch 12. Both gate drivers 21 and 22 perform gatedriving of their respective power transistor 11 and 12 based on PWMsignals LIN and HIN received from a microcontroller unit (MCU). The PWMsignals are control signals received from the MCU at PWM logic unit 35of the gate driver 20. The PWM logic unit 35 receives the LIN and HINsignals from the MCU and ensures there is a minimum dead timeimplemented to prevent bridge shoot through. Eventually, the respectivePWM signals are passed on to the respective low-side and high-side gatedriver 21 and 22, where the PWM signal HIN to the high-side gate driver22 is passed through a HV level shifter 25. After this point, thelow-side and high-side gate driver 21 and 22 perform gate driving.

Both gate drivers 21 and 22 include separate pre-driver circuitry 26 and27 and buffers 33 and 34, respectively. The pre-driver circuitries 26and 27 are configured to receive the PWM signals and, based thereon,control the on/off state of a respective first current source, such as asource FET, used to generate current Io+. Additionally, the pre-drivercircuitries 26 and 27 are configured to receive the PWM signals and,based thereon, control the on/off state of a respective second currentsource, such as a sink FET, used to generate current Io−. The respectivecurrent sources are provided in buffers 33 and 34. Thus, the buffers 33and 34 may each include a pair of complementary FETs used to generateturn-on currents Io+ and turn-off currents Io− for the respective powertransistor 11 and 12. Each of the pre-driver circuitries 26 and 27 mayfurther command a respective buffer 33 or 34 to use a certain currentcapability.

The LV gate driver 21 is arranged in a low-side region having lowvoltage domain, whereas the HV gate driver is arranged in high-sideregion having a high voltage domain. In practice, the gate driver 20also includes a termination region that isolates the high voltage domainfrom the low voltage domain, and may be referred to as an isolationtermination region. Thus, the termination region provides a high voltageisolation barrier between the two voltage domains.

The gate driver 20 may be configured to receive PWM control signals,from an MCU, and turn on or turn off respective transistors 11 and 12 inaccordance with the received PWM control signals. For example, duringthe turn-on process of a respective transistor 11 or 12, the gate driver20 may be used to provide (source) a gate current to the gate of therespective transistor 11/12 in order to charge the gate. In contrast,during the turn-off process, the gate driver 20 may be used to draw(sink) a gate current from the gate of the transistor 11/12 in order todischarge the gate.

Thus, the MCU is electrically coupled to the gate driver 20 for thetransmission of information and control signals therebetween, and thegate driver 20 is electrically coupled to the inverter leg 10 fordriving the power transistors thereof.

The three regions, the HV domain, the LV domain, and the terminationregion are monolithically built in a single integrated circuit. Thetechnology used to manufacture the gate driver 20 is capable of buildingall three regions on a single silicon die and build a single IC gatedriver. In between the HV domain and the LV domain is the terminationregion whose main purpose is to electrically isolate the HV domain andthe LV domain. The termination region in this specific technology (andin other high voltage technologies) includes a large diode usually usedas bootstrap diode 23 to charge a bootstrap capacitor 24. The levelshifter 25 is used to convert (i.e., level shift) the control signal,and thus transfer control information, from the low voltage/power domainto the high voltage/power domain.

In addition, Vb refers to the high-side floating supply voltage; Vsrefers to the high-side floating ground voltage; Vdd or Vcc refers tothe low-side and logic fixed supply voltage; Vss or Vee refers to alow-side ground voltage; HO refers to the high-side floating outputvoltage; LO refers to the low-side output voltage; DC+ refers to DC-linkpositive; DC− refers to DC-link negative; and HIN and LIN refers to thelogic input voltages (i.e., control signals) received from the MCU.

Typically, Vb=Vcc−Vs−Vd, where Vd is the voltage drop across thebootstrap diode 23. When Vcc=15V, Vs=0V, and the bootstrap diode 23 isforward biased and has a forward bias voltage drop of Vd=0.5V, thenVb=15V−0V−0.5V=14.5V That is, during normal operation Vb is about 15Vabove Vs due to the bootstrap capacitor 24 supplying to the high side.DC+, positive power supply rail, is typically in the range of 200-1200V,but not limited thereto. On top of this, Vs is equal to DC− (e.g., Vssor 0V) when the low side switch 11 is on (and switch 12 is off). DC− isa negative power supply rail and may be shorted to Vss, as shown, butneed not be. In this case, Vb is near 15V and the bootstrap capacitor 24is charging by Vcc through the bootstrap diode 23. Otherwise, Vs isequal to DC+ when the high side switch 12 is on (and switch 11 is off),in this case Vb is 15V above DC+ and the bootstrap capacitor 24 isslowly discharging, being that the bootstrap diode 23 is reverse biasedand non-conducting.

The aforementioned voltages are set such that the high-side voltagedomain operates in a higher voltage or power domain than that of thelow-side voltage domain. For example, the low-side (external) supplyvoltage Vcc may be set to 15V and the high-side supply voltage Vb may beoperated at a maximum voltage of 1215V when DC+ is 1200V.

The MCU, being coupled to the LV gate driver 21, is electrically coupledto the LV domain of the gate driver 20. Thus, the MCU is configured togenerate PWM control signals for controlling the transistors 11 and 12,and transmit the control signals to the gate driver 20 at the LV domain.For example, the gate driver 20 is configured to receive instructionsfrom the MCU to drive a motor phase (i.e., an inverter leg) connected tovoltage Vs using the PWM control signals. These PWM control signals arereceived by the gate driver 20 at the LV domain (i.e., at input pins HINand LIN) and passed through to the corresponding HV gate driver 22 andthe LV gate driver 21 via the appropriate logic (e.g., the PWM logic 35and, for the high-side, the level shifter 25). The LV gate driver 21 andthe HV gate driver 22 and are configured to receive the PWM controlsignals and drive the corresponding power transistor 11 and 12 viaoutput terminals HO and LO of the gate driver 20.

FIGS. 3A and 3B are schematic block diagrams of a power module 300according to one or more embodiments. The power module 300 in FIGS.3A-3C is a simplified block diagram which has only one inverter leg.However, multiple legs can be embodied in one package. The power module300 is similar to the power module 200 shown in FIG. 2 with theexception that power module 300 includes a surge voltage limitingelement 30 integrated within a module package 31 of the power module300.

As will be described herein, the surge voltage limiting element 30 maybe integrated at the package level of the power module 300, but outsideof the gate driver IC itself, as shown in FIG. 3A. Thus, in FIG. 3A, thesurge voltage limiting element 30 is provided inside the package 31 butnot on the gate driver IC 20. Alternatively, the surge voltage limitingelement 30 may be implemented at the silicon level of the gate driver IC(i.e., integrated in the gate driver IC 20 monolithically), as shown inFIG. 3B. Thus, in FIG. 3B, the surge voltage limiting element 30 isplaced inside the gate driver IC 20 with connections between the Nx andthe Vss pins made monolithically. Thus, even if the voltage limitingelement is located inside the driver IC, the two terminals of thevoltage limiting element are connected between the Nx and Vss (or Vdd)terminals by wire bonding. The Nx pin is connected to the low sideIGBT's emitter and the Vss pin is connected to Vss of the driver IC.

The surge voltage limiting element 30 is coupled between the emitter (orsource) terminal of the low-side power transistor 11 and a low-sidevoltage pin of the power module, where the low-side voltage pin is a pinof a leadframe of the power module 300 and is configured to be coupledto a low-side voltage source 32. Thus, the low-side voltage pin of thepower module is coupled to an outside connection, the outside connectionbeing a power source that is external to the power module.

The emitter (or source) terminal of the low-side power transistor 11 iscoupled to pin Nx of the power module 300. The Nx pin of the powermodule is a pin of a leadframe of the power module 300 and is coupled toan outside connection, the outside connection being external to thepower module and being coupled to a negative power supply rail of thesystem, directly or through current sensing element. Thus, the surgevoltage limiting element 30 is coupled between a low-side voltage pinand pin Nx of the leadframe of the power module.

The P pin of the power module is a pin of a leadframe of the powermodule 300 and is coupled to an outside connection, the outsideconnection being a positive bus input voltage, such as the positivepower supply rail DC+. In particular, the P pin is the name for themodule pin that is connected to the collector of high side powertransistor inside the power module.

In the example illustrated in FIG. 3A, the low-side voltage pin is a Vsspin coupled to voltage Vss (i.e., the low-side ground voltage, alsoreferred to as the low-side control negative supply).

In the alternative, the low-side voltage pin is a Vdd pin coupled tovoltage Vdd (i.e., the low-side and logic fixed supply voltage; alsoreferred to as the low-side control positive supply). This alternativeconnection is represented by a dashed line coupled to Vdd. Thus, thesurge voltage limiting element 30 is placed inside the package 31 whereit is coupled to the emitter (or source) terminal of the low-side powertransistor 11 and to either Vss or Vdd.

The surge voltage limiting element 30 may be any component capable oflimiting a surge voltage, and may be a capacitor or a clamp diode (e.g.,a diode clamping circuit), for example. The key provided with FIGS. 3Aand 3B show four example derivatives for the surge voltage limitingelement 30, including: (1) a capacitor, (2) a Zener diode, (3) two Zenerdiodes coupled in series, back-to-back (i.e., with their anodes coupledtogether), and (4) two Zener diodes coupled in series, facing each other(i.e., with their cathodes coupled together). One or more Zener diodescan also be replaced with a Transient Voltage Suppressor (TVS) in theseembodiments.

In addition, the surge voltage limiting element 30 may include anycombination of two or more derivatives (1)-(4) coupled in parallelbetween pins Vss and Nx. For example, the surge voltage limiting element30 may include two capacitors (i.e., derivatives (1) and (1)) coupledtogether in parallel between pins Vss and Nx. In another example, thesurge voltage limiting element 30 may include a capacitor and a Zenerdiode (i.e., derivatives (1) and (2)) coupled together in parallelbetween pins Vss and Nx. In another example, the surge voltage limitingelement 30 may include derivative (1) and derivative (3) coupledtogether in parallel between pins Vss and Nx. In another example, thesurge voltage limiting element 30 may include derivative (1) andderivative (4) coupled together in parallel between pins Vss and Nx.Other series or parallel combination variants are also available.

In the case that the low-side power transistor 11 is turned on, currentflows from the motor, through the low-side power transistor 11, and outof the pin Nx. Without the surge voltage limiting element 30, all thecurrent that flows through the low-side power transistor 11 exits thepower module 300 via pin Nx. Without being regulated, this exitingcurrent i may cause a surge voltage that is induced by a strayinductance of the printed circuit board (PCB) pattern and a shuntresistor. This induced surge voltage can damage the power module 300 dueto an electrical overstress failure. However, by integrating the surgevoltage limiting element 30 in parallel to this exiting current i, partof the exiting current is diverted, being routed through the surgevoltage limiting element 30 instead of entirely out of the pin Nx andthrough the stray inductance of the PCB. Thus, the surge voltage isreduced as a result of reducing the current exiting from pin Nx.

FIG. 3C is a schematic block diagram of the power module 300 of FIG. 3Awith additional circuitry coupled to DC−, the negative DC link supply,according to one or more embodiments. In particular, a shunt resistor Rsis provided between output pin Nx and DC− in order to provide a currentpath for the load current. Thus, when the low-side power transistor 11is on, the load current flows from the load (e.g., the motor), throughthe low-side power transistor 11, and through the shunt resistor Rs tothe negative power supply rail. A stray inductance L is also shown inthe external current path and represents the stray inductance of the PCB(not illustrated) to which the power module 300 and other externalcircuitry is placed.

Two parallel current branches, i1 and i2, are also depicted. Outputcurrent it is a portion of the load current that flows through thelow-side power transistor 11, exits pin Nx of the power module 300, andflows to the negative DC link, DC− (i.e., ground). In this example, thecollector/drain of the low-side power transistor 11 may be referred toas a first load path terminal of the transistor and the emitter/sourceof the low-side power transistor 11 may be referred to as a second loadpath terminal of the transistor. Thus, the load current flows throughthe transistor 11 from the first load path terminal to the second loadpath terminal when the transistor is turned ON. Thus, the second loadpath terminal, coupled to pin Nx, outputs the load current received fromthe motor, for example, when the low-side switch is turned ON and thehigh-side switch is turned OFF.

Current i2 is a portion of the load current that flows through thelow-side power transistor 11, flows through the surge voltage limitingelement 30, exits the power module 300 at a second pin of the powermodule 300, and flows to the negative DC link, DC− (i.e., ground). Thesecond pin is the Vss pin or the Vdd of the power module 300.

A surge voltage V_(SURGE) may be induced by current i1, where the surgevoltage V_(SURGE) is the sum of V_(R) and V_(L). However, by includingthe surge voltage limiting element 30 inside the package 31, some of thecurrent that flows through the low-side power transistor 11 is routedthrough the surge voltage limiting element 30 as current i2, effectivelyreducing current i1 (i.e., current i1 is reduced by current i2). Withcurrent i1 being reduced, the surge voltage V_(SURGE) induced by currenti1 is also reduced. Thus, the likelihood of failure of the power module300 can be reduced or prevented altogether. The above surge inducingmechanism is an example. When the low side switch is turned off, whenthe high side switch is turned off or when the high side switch isturned on, a similar phenomenon can happen, even the polarities of thecurrent and induced voltage can be different. The surge can be appliedbetween Nx and Vss. Any kind of surge voltage can also be protected bysurge voltage limit element 30.

Equations (1)-(4) demonstrate the reduction of the surge voltageV_(SURGE) based on the integration of the surge voltage limiting element30 inside the package 31.

$\begin{matrix}{V_{SURGE} = {V_{R} + V_{L}}} & {{eq}.\mspace{14mu}(1)} \\{V_{SURGE} = {{R \times i_{1}} + {L \times \frac{{di}_{1}}{dt}}}} & {{eq}.\mspace{14mu}(2)} \\{V_{SURGE} = {{R \times \left( {i - i_{2}} \right)} + {L \times \frac{d\left( {i - i_{2}} \right)}{dt}}}} & {{eq}.\mspace{14mu}(3)} \\{V_{SURGE} = {\left( {{R \times i} + {L \times \frac{di}{dt}}} \right) - \left( {{R \times i_{2}} + {L \times \frac{{di}_{2}}{dt}}} \right)}} & {{eq}.\mspace{14mu}(4)}\end{matrix}$

FIGS. 4A-4C are top-views of schematic block diagrams of power modules400 a, 400 b, and 400 c according to one or more embodiments. FIGS. 4Ato 4C are examples of module which have three phase in one modulepackage. Multiple packages are also available. In particular, FIGS.4A-4C illustrate different locations within the power module (i.e.,within the module package) at which the surge voltage limiting element30 can be integrated. While not shown in this example, it is assumedthat the power module 400 is incorporated into a single module package(e.g., module package 31 shown in FIGS. 3A-3C).

Turning to FIG. 4A, a power module 400 a includes gate driver IC 20arranged on and electrically coupled to a circuit substrate 41 (e.g., aprinted circuit board (PCB)). The power module 400 a further includes aleadframe 42 that is electrically coupled to the circuit substrate 41by, for example, bondwires. The circuit substrate 41 is mechanicallycoupled to a leadframe 42 by at least one coupling structure 43. Somecoupling structures 43 may provide an electrical connection.

In addition, multiple power transistor chips 44 and diode chips 45 areintegrated on the leadframe 42. The power transistor chips 44 mayinclude two groups 44 a and 44 b, where power transistor chips 44 ainclude low-side power transistors and power transistor chips 44 binclude high-side power transistors. Thus, each power transistor chip 44may include a low-side power transistor 11 or a high-side powertransistor 12, where multiple transistors 11 and multiple transistors 12are provided for a multi-phase system. In this example, threecomplementary pairs of power transistors for a three-phase system areprovided.

Additionally, each diode chip 45 may include a freewheeling diodecoupled to one of the power transistors. The diode chip 44 may includetwo groups 45 a and 45 b, where diode chips 45 a are coupled to acorresponding low-side power transistor and diode chips 45 b are coupledto a corresponding high-side power transistor.

Surge voltage limiting elements 30 are also integrated on the leadframe42 in a region (e.g., a low-side region) of the leadframe next to thelow-side power transistor chips 44 a. That is, the low-side powertransistor chips 44 a are interposed between the surge voltage limitingelements 30 and the high-side power transistor chips 44 b. Thus, thesurge voltage limiting elements 30 may be provided between the low-sidepower transistor chips 44 a and a periphery (i.e., an edge) of theleadframe 42.

A surge voltage limiting element 30 is provided for each low-side powertransistor chip (i.e., for each inverter leg), and coupled to theemitter (or source) of the corresponding low-side power transistor.Thus, since a three-phase system is shown, three surge voltage limitingelements 30 are provided.

Turning to FIG. 4B, FIG. 4B illustrates a power module 400 b that issimilar to power module 400 a, with the exception that the surge voltagelimiting elements 30 are integrated on the circuit substrate 41 near ornext to the gate driver IC 20.

Turning to FIG. 4C, FIG. 4C illustrates a power module 400 c that issimilar to power modules 400 a and 400 b, with the exception that thesurge voltage limiting elements 30 are integrated on gate driver IC 20.In other words, the surge voltage limiting elements 30 are addedmonolithically in the gate driver IC 20.

In view of the above, embodiments provide one or more voltage limitingelements inside a module package or monolithically inside the gatedriver IC, for example, silicon capacitors or trench capacitors. Thefewer number of voltage limiting element than the number of leg can beintegrated in one package. The voltage limiting elements are not limitedto capacitors but can be clamp diodes either physically embedded in themodule or monolithically embedded in the gate driver IC. Accordingly, anEOS robust device may be provided that provides higher quality powermodules and reduces the engineering cost associated with failureanalysis and root cause determination.

It will be appreciated that the gate driver IC 20 of the power modulemay be configured drive a low-side power transistor, both a high-sidepower transistor and a low-side power transistor, or multiple low-sidepower transistors, or any combination of driving one or more low-sidepower transistors with or without driving a high-side power transistor.In the case that the gate driver IC 20 does not drive one or morehigh-side power transistors, a separate gate driver IC may be integratedin the power module and used to drive the high-side power transistor(s).Regardless of configuration, a gate driver IC is used in combinationwith one or more surge voltage limiting elements 30 to reduce thecurrent exiting from pin Nx of the power module.

When considering the embodiment in which the surge voltage limitingelement 30 is integrated into a gate driver IC, and when furtherconsidering using separate voltage domains (e.g., LV and HV domains) inthe power module, the surge voltage limiting element 30 may beintegrated into the gate driver IC that drives the low-side powertransistor(s) (i.e., the gate driver IC that is located in the lowervoltage domain).

While various embodiments have been described, it will be apparent tothose of ordinary skill in the art that many more embodiments andimplementations are possible within the scope of the disclosure.Accordingly, the invention is not to be restricted except in light ofthe attached claims and their equivalents. With regard to the variousfunctions performed by the components or structures described above(assemblies, devices, circuits, systems, etc.), the terms (including areference to a “means”) used to describe such components are intended tocorrespond, unless otherwise indicated, to any component or structurethat performs the specified function of the described component (i.e.,that is functionally equivalent), even if not structurally equivalent tothe disclosed structure that performs the function in the exemplaryimplementations of the invention illustrated herein.

Furthermore, the following claims are hereby incorporated into thedetailed description, where each claim may stand on its own as aseparate example embodiment. While each claim may stand on its own as aseparate example embodiment, it is to be noted that—although a dependentclaim may refer in the claims to a specific combination with one or moreother claims—other example embodiments may also include a combination ofthe dependent claim with the subject matter of each other dependent orindependent claim. Such combinations are proposed herein unless it isstated that a specific combination is not intended. Furthermore, it isintended to include also features of a claim to any other independentclaim even if this claim is not directly made dependent to theindependent claim.

It is further to be noted that methods disclosed in the specification orin the claims may be implemented by a device having means for performingeach of the respective acts of these methods.

Further, it is to be understood that the disclosure of multiple acts orfunctions disclosed in the specification or in the claims may not beconstrued as to be within the specific order. Therefore, the disclosureof multiple acts or functions will not limit these to a particular orderunless such acts or functions are not interchangeable for technicalreasons. Furthermore, in some embodiments a single act may include ormay be broken into multiple sub acts. Such sub acts may be included andpart of the disclosure of this single act unless explicitly excluded.

Instructions may be executed by one or more processors, such as one ormore central processing units (CPU), digital signal processors (DSPs),general purpose microprocessors, application specific integratedcircuits (ASICs), field programmable logic arrays (FPGAs), or otherequivalent integrated or discrete logic circuitry. Accordingly, the term“processor,” as used herein refers to any of the foregoing structure orany other structure suitable for implementation of the techniquesdescribed herein. In addition, in some aspects, the functionalitydescribed herein may be provided within dedicated hardware and/orsoftware modules. Also, the techniques could be fully implemented in oneor more circuits or logic elements.

Thus, the techniques described in this disclosure may be implemented, atleast in part, in hardware, software, firmware, or any combinationthereof. For example, various aspects of the described techniques may beimplemented within one or more processors, including one or moremicroprocessors, DSPs, ASICs, or any other equivalent integrated ordiscrete logic circuitry, as well as any combinations of suchcomponents.

A control unit including hardware may also perform one or more of thetechniques described in this disclosure. Such hardware, software, andfirmware may be implemented within the same device or within separatedevices to support the various techniques described in this disclosure.Software may be stored on a non-transitory computer-readable medium suchthat the non-transitory computer readable medium includes a program codeor a program algorithm stored thereon which, when executed, causes acomputer program to perform the steps of a method.

Although various exemplary embodiments have been disclosed, it will beapparent to those skilled in the art that various changes andmodifications can be made which will achieve some of the advantages ofthe concepts disclosed herein without departing from the spirit andscope of the invention. It will be obvious to those reasonably skilledin the art that other components performing the same functions may besuitably substituted. It is to be understood that other embodiments maybe utilized and structural or logical changes may be made withoutdeparting from the scope of the present invention. It should bementioned that features explained with reference to a specific figuremay be combined with features of other figures, even in those notexplicitly mentioned. Such modifications to the general inventiveconcept are intended to be covered by the appended claims and theirlegal equivalents.

What is claimed is:
 1. A power module, comprising: a high-side powertransistor; a low-side power transistor coupled to the high-side powertransistor, the low-side power transistor comprising a first load pathterminal through which a load current enters the low-side powertransistor and a second load path terminal through which the loadcurrent exits the low-side power transistor; a gate driver integratedcircuit (IC) configured to drive at least one of the high-side powertransistor and the low-side power transistor; a leadframe having alow-side voltage pin configured to be coupled to a low-side voltagesource; a surge voltage limiting element coupled between the second loadpath terminal of the low-side power transistor and the low-side voltagepin, wherein the surge voltage limiting element comprises a firstterminal coupled to the second load path terminal and a second terminalcoupled to the low-side voltage pin; and a module package, wherein thehigh-side power transistor, the low-side power transistor, the gatedriver IC, the leadframe, and the surge voltage limiting element areencapsulated in the module package, wherein the first load path terminalis configured to receive the load current while the low-side powertransistor is turned on, and wherein, while the low-side powertransistor is turned on, the first terminal of the surge voltagelimiting element is configured to receive a first portion of the loadcurrent from the second load path terminal and the second terminal ofthe surge voltage limiting element is configured to output the firstportion of the load current to the low-side voltage pin, wherein thefirst portion of the load current is configured to flow from the secondterminal of the surge voltage limiting element to the low-side voltagepin and exit the module package from the low-side voltage pin.
 2. Thepower module of claim 1, wherein the low-side voltage pin is a Vss pinor a Vee pin.
 3. The power module of claim 1, wherein the low-sidevoltage pin is a Vdd pin or a Vcc pin.
 4. The power module of claim 1,wherein the second load path terminal is an emitter terminal or a sourceterminal.
 5. The power module of claim 1, wherein the leadframe includesa further pin configured to be coupled to a negative power supply rail,wherein a second portion of the load current is configured to exit themodule package from the further pin.
 6. The power module of claim 5,wherein the second load path terminal and the first terminal of thesurge voltage limiting element are coupled to the further pin.
 7. Thepower module of claim 5, wherein the first portion of the load currentis configured to exit the module package from the low-side voltage pinwhile the second portion of the load current exits the module packagefrom the further pin such that the first and the second portions of theload current concurrently exit the module package via two separate,parallel current paths.
 8. The power module of claim 1, wherein thefirst portion and a second portion of the load current are configured toflow towards the negative power supply rail in parallel current paths.9. The power module of claim 1, wherein the first terminal of the surgevoltage limiting element is coupled directly to the second load pathterminal of the low-side power transistor and the second terminal of thesurge voltage limiting element is coupled directly to the low-sidevoltage pin.
 10. The power module of claim 1, wherein the surge voltagelimiting element includes a capacitor, a Zener diode, or a combinationthereof.
 11. The power module of claim 1, further comprising: ahigh-side region that operates in a first voltage domain; and a low-sideregion that operates in a second voltage domain lower than the firstvoltage domain, wherein the low-side voltage source supplies power tothe low-side region.
 12. The power module of claim 1, wherein the surgevoltage limiting element, the high-side power transistor, and thelow-side power transistor are integrated on the leadframe.
 13. The powermodule of claim 12, wherein the low-side power transistor is interposedbetween the surge voltage limiting element and the high-side powertransistor.
 14. The power module of claim 1, further comprising: aprinted circuit board (PCB) on which the gate driver IC is arranged andelectrically coupled thereto, wherein the surge voltage limiting elementis integrated on the PCB.
 15. The power module of claim 1, furthercomprising: a printed circuit board (PCB) on which the gate driver IC isarranged and electrically coupled thereto, wherein the surge voltagelimiting element is integrated on the gate driver IC.
 16. The powermodule of claim 15, wherein the gate driver IC is configured to drivethe low-side power transistor.
 17. A power circuit, comprising: a powermodule, comprising: a high-side power transistor; a low-side powertransistor coupled to the high-side power transistor, the low-side powertransistor comprising a first load path terminal through which a loadcurrent enters the low-side power transistor and a second load pathterminal through which the load current exits the low-side powertransistor; a gate driver integrated circuit (IC) configured to drive atleast one of the high-side power transistor and the low-side powertransistor; a leadframe having a low-side voltage pin coupled to alow-side voltage source, and a further pin coupled to the second loadpath terminal of the low-side power transistor and to a negative powersupply rail; a surge voltage limiting element coupled between thelow-side voltage pin and the further pin, wherein the surge voltagelimiting element provides a first current path for a first portion ofthe load current that flows through the low-side power transistor,wherein the surge voltage limiting element comprises a first terminalcoupled to the second load path terminal and a second terminal coupledto the low-side voltage pin; and a module package, wherein the high-sidepower transistor, the low-side power transistor, the gate driver IC, theleadframe, and the surge voltage limiting element are encapsulated inthe module package, wherein the first load path terminal is configuredto receive the load current while the low-side power transistor isturned on, and wherein, while the low-side power transistor is turnedon, the first terminal of the surge voltage limiting element isconfigured to receive the first portion of the load current from thesecond load path terminal and the second terminal of the surge voltagelimiting element is configured to output the first portion of the loadcurrent to the low-side voltage pin; and an external circuit that isexternal to the power module and coupled to the further pin, wherein theexternal circuit provides a second current path for a second portion ofthe load current that flows through the low-side power transistor,wherein the first portion of the current is configured to flow from thesecond terminal of the surge voltage limiting element to the low-sidevoltage pin and exit the module package from the low-side voltage pin.18. The power circuit of claim 17, wherein the first current path andthe second current path are parallel current paths interposed betweenthe second load path terminal of the low-side power transistor and thenegative power supply rail.
 19. The power circuit of claim 17, whereinthe surge voltage limiting element includes a capacitor, a Zener diode,or a combination thereof.
 20. The power module of claim 17, wherein thefirst portion of the load current is configured to flow through thesurge voltage limiting element while the low-side power transistor isturned on.
 21. The power circuit of claim 17, wherein the first portionof the load current is configured to exit the module package from thelow-side voltage pin while the second portion of the load current exitsthe module package from the further pin such that the first and thesecond portions of the load current concurrently exit the module packagevia two separate, parallel current paths.
 22. The power circuit of claim21, wherein the external circuit comprises a stray inductance and acurrent limiting element connected in series between the further pin andthe negative power supply rail.